TMDXEVM5515【PDF 11/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range

FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status

register is set through software, the on-chip ROM is disabled and not present in the memory map, and

byte address range FE0000h – FFFFFFh is unmapped. A hardware reset always clears the MPNMC bit,

so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect

the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is

a one cycle per word access memory.

2.2.4

2.2.5

External Memory

The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The

external memory space is divided into five chip select spaces: one dedicated to SDRAM and mobile

SDRAM (EMIF CS0 or CS[1:0] space), and the remainder (EMIF CS2 through CS5 space) dedicated to

asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called

EM_CSx) that is activated during an access to the chip select space.

The external memory interface (EMIF) provides the means for the DSP to access external memories and

other devices including: mobile single data rate (SDR) synchronous dynamic RAM (SDRAM and

mSDRAM), NOR Flash, NAND Flash, and asynchronous static RAM (SRAM). Before accessing external

memory, you must configure the EMIF through its memory-mapped registers.

The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 5

dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pins of the

EMIF can be operated at an independent voltage from the other I/O pins on the device.

I/O Memory

The device includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and

system registers used for idle control, status monitoring and system configuration. I/O space is separate

from program/memory space and is accessed with separate instruction opcodes or via the DMA's.

Table 2-4 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O

space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor

DMA. For the expanded tables of each peripheral, see Section 5 , Peripheral Information and Electrical

Specifications of this document.

Some of the DMA controllers have access to the I/O-Space memory-mapped registers of the following

peripherals registers: I2C, UART, I2S, MMC/SD, EMIF, USB, and SAR ADC.

Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is

not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the

Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).

Copyright ? 2010–2013, Texas Instruments Incorporated

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